1. Field of the Invention
The present invention relates generally to coreless packaging substrates and methods for fabricating the same, and more particularly, to a coreless, ultra-fine pitch packaging substrate and a method for fabricating the same.
2. Description of Related Art
Along with the development of electronic industries, electronic products have a trend towards miniaturization and high performance, and accordingly multi-layer boards are developed so as to increase the layout area for the layout through interlayer connection techniques, and meet demands for high-density integrated circuits and meanwhile reduce the thickness of packaging substrates.
Conventionally, a multi-layer board comprises a core board and built-up structures disposed on two sides of the core board. However, the use of the core board increases the length of wires and thickness of the overall structure. Accordingly, coreless boards are developed to overcome these drawbacks, thereby meeting the developmental trend of high frequency and miniaturization.
FIGS. 1A to 1F shows a conventional packaging substrate and a method for fabricating the same.
Referring to FIG. 1A, a carrier board 10 is provided, and a thin metal layer 11, a releasing layer 12 and a carrier metal layer 13 are formed in sequence on the two surfaces of the carrier board 10.
Referring to FIG. 1B, a first dielectric layer 14 is formed on the carrier metal layer 13.
Referring to FIG. 1C, a plurality of vias 140 is formed in the first dielectric layer 14 by photolithography or laser ablation, and portions of the carrier metal layer 13 exposed from the vias 140 are etched away so as to form a plurality of concave portions 130.
Referring to FIG. 1D, a plurality of solder bumps 141a and first conductive vias 141b are formed in sequence in the concave portions 130 and the corresponding vias 140, and a first wiring layer 142 is formed on the first dielectric layer 14 and electrically connecting to the first conductive vias 141b; subsequently, a built-up structure 15 is formed on the first dielectric layer 14 and the first wiring layer 142, wherein the built-up structure 15 comprises at least a second dielectric layer 151, a second wiring layer 152 formed on the second dielectric layer 151, and a plurality of second conductive vias 153 formed in the second dielectric layer 151 and electrically connecting to the first wiring layer 142 and the second wiring layer 152, the outermost second wiring layer 152 of the built-up structure 15 comprising a plurality of conductive pads 154; furthermore, an insulating protective layer 16 is formed on the outermost layer of the built-up structure 15, and a plurality of openings 160 corresponding in position to the conductive pads 154 are formed in the insulating protective layer 16 so as for the conductive pads 154 to be exposed from the openings 160 formed in the insulating protective layer 16, respectively.
Referring to FIG. 1E, the releasing layer 12 is separated from the carrier metal layer 13 so as to form initial coreless packaging substrates that are separated from the carrier board 10.
Referring to FIG. 1F, the carrier metal layer 13 is removed such that the solder bumps 141a protrude from the first dielectric layer 14. Thus, a coreless packaging substrate is obtained, wherein the solder bumps 141a can be used for mounting a semiconductor chip (not shown) and the conductive pads 154 can be used for mounting a printed circuit board (not shown).
In the above-described method, since the carrier metal layer 13 is made of a metal material, the concave portions 130 can only be formed by etching. The etch-induced diameter and depth deviations make it difficult to control the volume and height deviation of the solder bumps 141a to be formed subsequently in the concave portions 130, thus leading to poor coplanarity of the solder bumps 141a. As a result, the joints between the semiconductor chip and the solder bumps may be damaged due to unbalanced stresses, or portions of the electrode pads of the semiconductor chip cannot form reliable joints with the corresponding solder bumps 141a due to insufficient height of the solder bumps 141a. In addition, if the average volume or height of the solder bumps 141a is relatively large, solder bridging (short circuit) may occur during reflow of the solder bumps 141a. 
Therefore, it is imperative to overcome the above drawbacks of the prior art.